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| Features * * * * * * * * * * Single Voltage Operation - 5V Read - 5V Reprogramming Fast Read Access Time - 45 ns Internal Program Control and Timer 8K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 10 s/Byte Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation - 30 mA Active Current - 100 A CMOS Standby Current Typical 10,000 Write Cycles Description The AT49F010/HF010 are 5-volt-only in-system programmable and erasable Flash Memories. Their 1-megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 45 ns (HF version) with a power dissipation of just 165 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 A. To allow for simple in-system reprogrammability, the AT49F010/HF010 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F010/HF010 is performed by erasing the entire 1 megabit of memory and then programming on a byte by byte basis. The byte programming time is a fast 50 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte pro- 1-Megabit (128K x 8) 5-volt Only CMOS Flash Memory AT49F010 AT49HF010 AT49F010/HF010 Pin Configurations Pin Name A0 - A16 CE OE WE Function Addresses Chip Enable Output Enable Write Enable DIP Top View (continued) I/O0 - I/O7 Data Inputs/Outputs NC No Connect PLCC Top View TSOP Top View Type 1 0852AX-5/97 gram cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, Block Diagram Device Operation READ: The AT49F010/HF010 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 128K bytes memory array (or 120K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-by-byte basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cy2 cle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. AT49F010/HF010 AT49F010/HF010 PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F010/HF010 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e AT49F010/HF010 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F010/HF010 in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. Command Definition (in Hex) Command Bus Sequence Cycles Read Chip Erase Byte Program Boot Block (1) Lockout Product ID Entry Product ID (2) Exit Product ID (2) Exit 1 6 4 6 3 3 1 1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA F0 2nd Bus Cycle Addr 2AAA 2AAA 2AAA 2AAA 2AAA Data 55 55 55 55 55 3rd Bus Cycle Addr 5555 5555 5555 5555 5555 Data 80 A0 80 90 F0 4th Bus Cycle Addr 5555 Addr 5555 Data AA DIN AA 5th Bus Cycle Addr 2AAA Data 55 6th Bus Cycle Addr 5555 Data 10 2AAA 55 5555 40 Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH. 2. Either one of the Product ID exit commands can be used. Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to V CC + 0.6V Voltage on OE with Respect to Ground ................... -0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 DC and AC Operating Range AT49HF010-45 AT49HF010-55 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 10% 0C - 70C -40C - 85C 5V 10% AT49F010-70 0C - 70C -40C - 85C 5V 10% AT49F010-90 0C - 70C -40C - 85C 5V 10% AT49F010-12 0C - 70C -40C - 85C 5V 10% Operating Modes Mode Read Program (2) CE VIL VIL VIH X X X OE VIL VIH X (1) X VIL VIH WE VIH VIL X VIH X X Ai Ai Ai X I/O DOUT DIN High Z Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware Software (5) High Z A1 - A16 = VIL, A9 = VH, (3) A0 = VIL A1 - A16 = VIL, A9 = VH, (3) A0 = VIH A0 = VIL, A1 - A16 = VIL A0 = VIH, A1 - A16 = VIL Manufacturer Code (4) Device Code (4) Manufacturer Code (4) Device Code (4) VIL VIL VIH Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 1FH, Device Code: 17H 5. See details under Software Product Identification Entry/Exit. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC (1) VIL VIH VOL VOH1 VOH2 Note: Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Com. Ind. Com. Ind. Min Max 10 10 100 300 3 30 40 0.8 Units A A A A mA mA mA V V V V V 2.0 IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 .45 1. In the erase mode, ICC is 90 mA. 4 AT49F010/HF010 AT49F010/HF010 AC Read Characteristics AT49HF010-45 AT49HF010-55 Symbol tACC tCE (1) tOE (2) tDF (3, 4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first Min Max Min Max AT49F010-70 Min Max AT49F010-90 Min Max AT49F010-12 Min Max Units ns ns ns ns ns 0 0 45 45 25 25 0 0 55 55 30 25 0 0 70 70 35 25 0 0 0 90 90 40 25 0 0 0 120 120 50 30 AC Read Waveforms (1, 2, 3, 4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load 45 ns / 55 ns 70/90/120 ns tR, tF < 5 ns Pin Capacitance (f = 1 MHz, T = 25C) (1) Typ CIN COUT Note: Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 4 8 1. This parameter is characterized and is not 100% tested. 5 AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 50 0 90 Max Units ns ns ns ns ns ns ns ns AC Byte Load Waveforms WE Controlled CE Controlled 6 AT49F010/HF010 AT49F010/HF010 Program Cycle Characteristics Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds Program Cycle Waveforms Chip Erase Cycle Waveforms Note: OE must be high only when WE and CE are both low. 7 Data Polling Characteristics Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Write Recovery Time (1) Min 10 10 0 Typ Max Units ns ns ns ns Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time (1) Min 10 10 150 0 Typ Max Units ns ns ns ns ns OE to Output Delay (2) OE High Pulse Write Recovery Time Toggle Bit Waveforms Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. (1, 2, 3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 8 AT49F010/HF010 AT49F010/HF010 Software Product (1) Identification Entry LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE (2, 3, 5) Boot Block Lockout (1) Feature Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA Software Product (1) Identification Exit LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE (4) LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second (2) Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. Notes for software product identification: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A16 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 17H 9 Ordering Information (1) tACC (ns) 45 ICC (mA) Active Standby Ordering Code AT49HF010-45JC AT49HF010-45PC AT49HF010-45TC AT49HF010-45JI AT49HF010-45PI AT49HF010-45TI AT49HF010-55JC AT49HF010-55PC AT49HF010-55TC AT49HF010-55JI AT49HF010-55PI AT49HF010-55TI AT49F010-70JC AT49F010-70PC AT49F010-70TC AT49F010-70JI AT49F010-70PI AT49F010-70TI AT49F010-90JC AT49F010-90PC AT49F010-90TC AT49F010-90JI AT49F010-90PI AT49F010-90TI AT49F010-12JC AT49F010-12PC AT49F010-12TC AT49F010-12JI AT49F010-12PI AT49F010-12TI Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) 30 0.1 40 0.1 55 30 0.1 40 0.1 70 30 0.1 40 0.3 90 30 0.1 40 0.3 120 30 0.1 40 0.3 Note: 1. The AT49F010/HF010 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Package Type 32J 32P6 32T 32 Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32 Lead, Thin Small Outline Package (TSOP) 10 AT49F010/HF010 |
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